This invention relates to methods and apparatus for deriving valid data signals in a video computer and the like, and more particularly relates to improved methods and apparatus for preventing the transfer of spurious or invalid signals from the video storage circuit to the microprocessor and the like.
It is conventional, in a video computer system, to employ a data storage circuit comprising a RAM chip having a serial shift register. In such an arrangement, the microprocessor is programmed to generate row and column address signals to establish the RAM chip in a parallel mode, and thereafter to generate appropriate "read" and transfer signals to transfer the selected data to the parallel output terminal of the storage circuit. Similarly, the RAM chip is established in the serial mode by the transfer and row address signals, and the selected data is then transferred to the shift register in response to the "read" signal. Thereafter, a clocking signal from the microprocessor may be used to clock out the data from the shift register to the serial output terminal of the storage circuit.
Data bits on the serial output terminal are directed to the CRT circuit for producing a video image. However, data bits at the parallel output terminal are intended to be redelivered to the microprocessor for use in the selected program. Accordingly, it is essential to the purposes of the microprocessor that it receive only valid and not spurious signals from the parallel output terminal of the data storage circuit.
It should be noted, however, that in a system of the type described in said U.S. Pat. No. 4,663,735, after data is transferred to the parallel output terminal in response to the "read" and transfer signals, another row address signal may appear before the transfer signal has been discontinued by the microprocessor. As hereinbefore indicated, this simulates the condition wherein the RAM chip is in the serial mode, and if a "write" signal also happens to occur or be present at this time, the effect is that data in the shift register may be transferred into the particular memory cell from which data has just previously been transferred to the parallel output terminal. Since the RAM chip is actually in the parallel mode, however, there is a likelihood that this unwanted or spurious data will not lodge in the cell of interest, but will also appear at the parallel output terminal at or about the same time as the valid data of interest.
These disadvantages in the prior art are overcome by the present invention, and improved methods and apparatus for covering stored data signals are provided, which not only deliver valid signals to the microprocessor, but which prevent any unwanted or spurious signal from being delivered to the parallel output terminal at about the same time.